1. Field of the Invention
The present invention relates to semiconductor devices and data write methods.
2. Description of the Related Art
Flash memories are being widely used as non-volatile memories that can electrically rewrite data. However, the time required for rewriting data in a flash memory is very much longer than that in a semiconductor memory device such as a DRAM or SRAM. Moreover, the controller that controls a flash memory cannot access the flash memory while data is being rewritten.
To solve the above problems, a flash memory of a dual operation type has been developed recently. Such a flash memory has its inside divided into banks, and can read data from one of the banks while rewriting data in another one of the banks. Here, a “bank” is a block or the group consisting of two or more arbitrarily combined blocks, and “banks” are memory banks that can perform data processing at the same time.
Next, a conventional flash memory of the dual operation type is described. FIG. 1 is a block diagram of the conventional flash memory of the dual operation type. As shown in FIG. 1, the flash memory 1 includes a cell array 2, a read sense amplifier 3, a write sense amplifier 4, and a write amplifier 5. The cell array 2 includes banks BANK0 through BANKn. The memory cells of each of the banks BANK0 through BANKn is managed by the sector. Y-gates 21 are connected to read data buses RDB0 through RDBm and write data buses WDB0 through WDBm.
The read sense amplifier 3 reads data from the memory cells via the read data buses RDB0 through RDBm. The write sense amplifier 4 reads verified data from the memory cells via the write data buses WDB0 through WDBm. The write amplifier 5 writes data into the memory cells via the write data buses WDB0 through WDBm. In this flash memory of the dual operation type, data can be read from a bank while data is rewritten in another bank.
Such a flash memory of the dual operation type is disclosed in U.S. Pat. No. 6,240,040.
In the above flash memory 1 of the dual operation type, however, high-speed writing cannot be performed, because, in a case where an internal power supply is employed, the number of bits that can be written at once is limited by the restriction on the current capacity of the high-voltage generating circuit mounted on the chip. If high-speed writing is to be performed using an external power supply, a large number of bits can be written at once, as there is no limitation on the number of bits that can be written at once. However, to write a large number of bits at once, the same number of write data buses as the number of bits are required. As the number of write data buses increases, the chip size also increases, which is not desirable.